Model order reduction techniques for circuit simulation

Theoretical and practical aspects of model order reduction techniques for use in the context of circuit simulation are investigated, with particular attention to problems involving clocked analog circuitry and to interconnect and packaging applications. First, an algorithm for the efficient simulation of clocked analog circuits is described and simulation results are presented. Traditional simulation programs, which must accurately solve the associated differential equations with a time discretization method become extraordinarily computationally expensive when applied to simulating the transient behavior of clocked analog circuits. These circuits are clocked at a frequency whose period is typically orders of magnitude smaller than the time interval of interest to the designer. The nature of the calculations requires that in order to construct the solution over the time interval of interest, an accurate solution must be computed for every cycle of the high frequency clock in the interval, and this can involve thousands of cycles. The algorithm to be described substantially reduces the simulation time without compromising accuracy by exploiting the property that the behavior of such a circuits in a given high frequency clock cycle is similar, but not identical, to the behavior in the preceding and following cycles. This algorithm is in itself a model order reduction technique, since it simplifies the understanding of the problem and reduces its computational cost. Further model order reduction is possible which allows for significant speedups in circuits containing digital control circuitry. Next, we describe an algorithm for efficient PICE-level simulation of frequencydependent elements, such as transmission lines with arbitrary scattering parameter descriptions, or complicated 3-D interconnect with nonlinear transistor drivers and receivers. The elements can be represented in the form of a frequency-domain model or a table of measured frequency-domain data. Our approach initially uses a forced stable decade-by-decade 2 minimization approach to construct a sum of rational functions approximation, which may have dozens of poles and zeros. This unnecessarily high-order model is then reduced using a guaranteed stable model order reduction scheme based on balanced realizations. Once the reduced-order model is derived, an impulse response can easily be generated. Finally, the impulse response can be efficiently incorporated into a circuit simulator using recursive convolution. Examples including a transmission line